As print resolutions increase in electrophotographic-based (EP) printers, print smoothing methods may have less effect on perceived print quality. As print standards move closer to camera ready copy, EP printers are typically forced to make a crucial tradeoff between image definition and smoothness. To achieve a sharper more clearly defined image, each halftone cell must occupy only a small absolute area, corresponding to a small grid of printed pels. To achieve a smooth and gradual transition in gray levels, as are required for lifelike fleshtones, each halftone cell must contain a high number of available gray levels from which to choose. Additionilly, for binary printing where one bit of information represents a black or white pel, the user must choose between image definition and smoothness.
Multi-bit or continuous tone (contone) printing avoids the difficult tradeoff between definition and smoothness by providing multiple levels of control per printed pel. By allowing the image generation software to select multiple intermediate levels, the number of printable gray levels in a given region is greatly increased. For example, given a halftone cell comprised of a 4.times.4 array of pels, seventeen levels of gray {(4*4)+1=17} are possible, including white and black. However, if each pel in this halftone cell can be further divided into four subdivisions, then 65 levels of gray {(4*4*4)+1=65} are possible, and by providing more subdivisions per pel, the effective resolution of the printer is increased.
In an effort to increase perceived print resolution, printer hardware designs have focused on methods to divide each printed pel into successively smaller pieces called slices. The increase in division of the pels has typically been achieved by increasing the frequency at which the slice-based clock runs, thereby providing more slices per pel. This method is achievable for standard ASIC silicon processes for 300 dpi printing and 600 dpi printing on slow to medium process-speed printers (e.g., 16 pages per minute (PPM) or less). However, on faster 600 dpi printers and on 1200 dpi and above printers, the clock frequency required to divide each pel into many slices becomes prohibitively last. For example, to divide a 1200 dpi pel into eight slices at 12 PPM would require a slice-based clock frequency of about 320 MHz, which is simply beyond the practical upper limit achievable in today's commodity ASIC silicon processes.
Since traditional synchronous or clock-based methodologies cannot provide the required level of performance, the hardware must be designed to use asynchronous design techniques. One such technique involves the use of analog delay lines, but this implementation is difficult in practical application, due to the variability in the delay produced by a given delay element. In a standard commodity ASIC, the time delay obtained at a desired setting can vary by a factor of three to four times with respect to all variations in silicon processing, ambient temperature, and power supply voltages. This variability must be greatly reduced before the use of delay lines in conventional circuits is practical in providing increased print resolution.
A separate custom delay line module could be used to provide repeatable delay times that could be used to further subdivide a slice. Alternatively, the use of analog pulse width techniques could be useful in an EP printer system, perhaps by using a separate analog pulse width generation device such as a pulse width modulator chip, part number AD9560, manufactured by Analog Devices, or a programmable pulse generator, part number DS1040, manufactured by Dallas Semiconductor.
Other methods of using delay elements in image processing systems or in printers are disclosed in patents, such as U.S. Pat. No. 5,379,126 (by Seto), which discloses an image processing system having high tone quality. A master clock signal is synchronized with an eight-bit image input signal. Using latches and delay circuits, the density level value of the image signal can be modified. This is done by weighting certain bits by the delay time of one or more delay clocks, and also the number of tones per input image signal. In one embodiment, four different delayed clock signals, each having a phase different from the master clock, are used to drive a "changeover" circuit that accepts the image signal as an input along four different parallel lines output from a latch circuit. These parallel image signals are combined with the clock signals to provide a weighted tone signal for each byte of image data. The phase angles of the four different "sub-pel" clock signals are fixed by a set of pre-determined time delay elements.
U.S. Pat. No. 5.351,137 (by Kato) discloses a pixel density converting system for pixel density of an image that includes pseudo halftone processed images and characters or line drawings in a mixed state. The pixel density can either be increased or decreased by various methods that are disclosed in this patent. In some cases, the image signal is sent through line buffers, and then through delay flip-flop elements that are clocked by an image clock. In the illustrated embodiments, the "D" flip-flops are grouped in rows of four and columns of four, to provide a precision of sixteen (16) pixels that can be referred to.
U.S. Pat. No. 5,488,487 (by Ojima) discloses an image forming system for use with laser printers that inputs a signal that becomes subject to pulse-width modulation at a time period that is shorter than the period of the main clock signal. The input signal is converted into a plurality of different signals each having a length of time shorter than the clock signal, thereby performing pulse-width modulation according to a predetermined weighting. Highly toned signals can be obtained without increasing the frequency of the clock signal. In the first embodiment, a single ninety degree phase delay circuit is provided, thereby creating a quadrature clock. In the second embodiment, the pulse-width modulation weighting is not equally divided, but instead the time delay is adjusted by non-uniform increments. Ojima states that, "as long as stable operation of the changeover circuit elements is assured, the present invention is not limited as to the number of delay clock signals and the phase differences among them." This "stable operation," of course, assumes that the time delay circuits themselves will not change operating characteristics over various conditions.
U.S. Pat. No. 4,681,424 (by Kantor) discloses an EP printer that uses an "environmental control signal" (ECS) to determine the overall gray exposure for a particular pel to be printed. Both the leading and trailing edges of the pel can be shifted in time, so as to be compensated for changes in environmental conditions. A delay line circuit has five separate outputs that are connected to a series of selector circuits. A set of comparators have their output states controlled by the voltage level of the current environmental control signal. The outputs of these comparators control how much delay will be used on the trailing edge of a black pel, to increase its overall width. Similarly, the outputs of these comparators also determine the timing of the leading transition of the same pel. The delay line produces a set of progressively delayed pulses with respect to the original clock signal, and the compensation for environmental conditions automatically chooses which of the delay line outputs will be used based upon the analog voltage of the ECS signal.
U.S. Pat. No. 4,625,222 (by Bassetti) discloses print enhancement circuits for an EP printer that modify the drive signals for the printhead. Modifications include smoothing the digitized edges of slanted lines, broadening single pel width lines in the direction perpendicular to the scan direction as well as in the direction parallel to the scan. The circuits disclosed use shift registers and variable time delay elements as delay lines to change the density of gray signals used for pels. Leading and trailing edge gray signals are provided next to black data in a direction parallel to the scan while expanded black signals are provided for the single pel data in a direction perpendicular to the scan. Depending upon the mode of operation, the black and gray signals may both be passed, or if a single pel area contains two gray signals only the leading gray signal is passed, or if a single pel area contains two added black signals and a gray signal, only the gray signal is passed (there are several variations disclosed).
U.S. Pat. No. 4,544,264 (by Bassetti) discloses a similar circuit as in Bassetti '222 in that it discloses delay circuits for producing leading or trailing black signal information to broaden the width of a single pel. In general, a gray pel is always added on one edge of a black line, and this disclosure shows the gray pel always being added adjacent the trailing edge of the black line. Bassetti '264 inhibits gray pels at places where black pels are also being added in the same location.